1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a ferroelectric memory cell array devised to reduce RC load of a plate line.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, such as a ferroelectric random access memory (FRAM), can have a data accessing speed equal to that of a dynamic random access memory (DRAM). In addition, a nonvolatile ferroelectric memory can retain data even when the power is off. For these reasons, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM is a memory device similar in structure to that of the DRAM in that both devices include a capacitor. Unlike the DRAM, the capacitor of an FRAM includes a ferroelectric substance having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even after an electric field is removed from a ferroelectric capacitor.
FIG. 1 illustrates a hysteresis loop for a ferroelectric substance. Even after an electric field that induced a polarization has been removed, data is maintained to a certain amount, as shown by points d and a in FIG. 1. The removal of power does not erase data due to the presence of residual polarization or spontaneous polarization that maintains charge in the ferroelectric capacitor. Thus, a nonvolatile ferroelectric memory cell, such as a ferroelectric random access memory that includes cells each having a transistor and a ferroelectric capacitor, can be used as a memory device by corresponding states of charge to “1” and “0”, respectively. For example, a ferroelectric capacitor having a charge in a state shown as d in FIG. 1 can be a “1” and a ferroelectric capacitor having a charge in a state shown as a in FIG. 1 can be a “0”.
As shown in the circuit diagram of FIG. 2, a related art nonvolatile ferroelectric memory array includes first and second bitlines BL1 and BL2 formed in one direction that cross first and second split wordlines SWL1 and SWL2 formed in a second direction. At the intersection of a pair of the split wordlines and a bit line a memory cell is formed. The memory cell includes a first transistor T1 with a gate connected to the first split wordline SWL1 and a source connected to the first bitline BL1, and a first ferroelectric capacitor FC1 with one terminal connected to a drain of the first transistor T1 and the other terminal connected to the second split wordline SWL2. The nonvolatile ferroelectric memory array, as shown in FIG. 2, further includes a second transistor T2 with a gate connected to the second split wordline SWL2 and a source connected to the second bitline BL2, and a second ferroelectric capacitor FC2 with one terminal connected to a drain of the second transistor T2 and the other terminal connected to the first split wordline SWL1.
FIG. 3 is a timing diagram illustrating data input/output operation of a related art nonvolatile ferroelectric memory array. The period t0 is for precharging all bitlines to a ground level of 0V in response to a high signal. During the period t0, the first and second split wordlines SWL1 and SWL2 are not yet activated to a high state.
Subsequently, in the period t1, both of the first and second split wordlines SWL1 and SWL2 are activated to the high state and thus the voltage level of the bitlines can change. In the instance where the ferroelectric capacitor stores a high state, an electric field is provided from the ferroelectric capacitor having greater potential than the bitlines. Accordingly, a large amount of current flows as ferroelectric polarization changes, and thus high voltage is at the bitlines. In the instance where the ferroelectric capacitor stores a low state, an electric field is provided from the ferroelectric capacitor having about same potential as the bitlines. Accordingly, a small amount of current flows since ferroelectric polarization does not change, and thus a low voltage is at the bitlines.
As shown in the period t2 of FIG. 3, when cell data is transferred to the bitlines, both the first and second split wordlines SWL1 and SWL2 are in the “on” state, a sense amplifier is activated that switches an active signal to a high state to amplify the bitline level. Then, in the period t3, a column switch signal CS goes to a high state such that a switch is activated to connect bitlines and data bus lines to each other. By connecting the bitlines and data bus lines, bitline data can be transmitted to data bus in a read mode and/or data bus data can be transmitted to bitlines for a write mode of a logic state “1” in a cell during the period t3. For example, if the second bitline BL2 is in a high state, a logic “1” state is stored in the ferroelectric capacitor FC2 of the cell because of the electrical potential between the low state of the first split wordline SWL1 and the high state of the second bitline BL2.
In the period t4, the first and second bitline BL1 and BL2 can write a logic ‘0’ into the respective ferroelectric capacitors FC1 and FC2 by making the first split wordline SWL1 be in a high state while transmitting a logic “0” state, such as a low state signal, onto the bitline. On the other hand, if the first and second bitlines BL1 and BL2 are in a high state during period t4, cell data does not change.
Subsequently, in the period t5, the first split wordline SWL1 is switched to a high state and the second split wordline SWL2 is switched to a low state. Accordingly, the first transistor T1 is turned on, and if the first bitline BL1 is in the high state, a high state, such as a logic ‘1’ state, is stored in the ferroelectric capacitor FC1 between the low state of the second split wordline SWL2 and the high state of the first bitline BL1. Lastly, the period t6 is a precharge period to prepare for the next cycle of operation.
In the related art, to operate cells, split wordlines are provided with two types of pulses that are indicative of whether a split wordlines should function as a wordline WL or a plate line. For this reason, the layout area for buses and drivers for wordline and plate line functions are increased. Accordingly, the size of the device itself increases and the speed decreases because of increased distances between components.